In the field of electrostatic discharge protection, it is known to provide, for example for automotive applications, a stack of low-voltage protection devices including a first NPN bipolar transistor serially coupled to a second NPN bipolar transistor. Each of the first and second NPN bipolar transistors is self-biased, the first and second NPN transistors having respective trigger voltages of, for example, 45V. The first and second NPN transistors are selected and configured so as to provide a trigger voltage, Vt1, above which an ESD event causes the first and second transistors to conduct resulting in the ESD event being short-circuited through the first and second NPN transistors to, for example, ground potential.
However, an interconnecting node between the first and second NPN bipolar transistors “floats”, i.e. does not remain at a constant potential, and so when an Electromagnetic Interference or a fast transient event occurs, parasitic elements, for example parasitic capacitances of the first and second NPN transistors, cause an imbalance in the voltage applied across the first NPN transistor and the second NPN transistor.
Consequently, the potential across the first NPN transistor can, for example, reach 45V, whereas the potential across the second NPN transistor only reaches 15V. In such a situation, the serially coupled first and second NPN transistors behave unexpectedly. In this respect, once the first NPN transistor has switched on, the potential across the first transistor falls to a snapback voltage of the first NPN transistor, for example 13V, resulting in the potential across the second NPN transistor subsequently rising to the trigger voltage, for example the 45V level mentioned above, due to the resistive properties of the second NPN transistor when not triggered. Hence, undesirably, the second NPN transistor is triggered into an activated state. Consequently, both the first and second NPN transistors are latched into “on” states even though the combined trigger voltage, Vt1, has not been reached, resulting in sustained current flow through both the first and second NPN transistors subsequent to the occurrence of the Electromagnetic Interference or the fast transient event. The sustained current flow through the stack either destroys the stack or prevents a circuit that is protected by the stack from functioning correctly.